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19-2098; Rev 1; 1/02
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater
General Description
The MAX3754/MAX3755 quad-port bypass circuits (PBCs) are designed for use in Fibre Channel Arbitrated Loop applications. Each consists of four serially connected port bypass circuits and a repeater that provides clock and data recovery. The quad-PBC allows connection of up to four Fibre Channel L-ports; each can be enabled or bypassed by individual logic inputs. To reduce the external parts count, all signal inputs and outputs have internal termination resistors. The MAX3754/MAX3755 comply with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit intervals (UIs) of high-frequency jitter. These devices operate from a single +3.3V supply.
Features
o Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate Operation o Meets Fibre Channel Jitter Tolerance o 1400mV Typical Differential Output Swing o 3.0V to 3.6V Operation o No Reference Clock Required o Frequency Lock Indication o 1W Power Consumption (MAX3754) at +3.3V o 150 or 100 Differential L-Port Impedance Available
MAX3754/MAX3755
Applications
LOUT2+ LOUT2-
Pin Configuration
GND GND LOUT3+ LOUT3GND LIN3+
40 39 38
1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Fibre Channel Data Storage Systems Storage Area Networks Fibre Channel Hubs
GND LIN1LIN1+ GND LOUT11 2 3 4 5 6 7 8 9 10 11 12
GND LIN2+ LIN2-
48
47
46
45
44
43
42
41
37
LIN3-
36 35 34 33 32
GND LOUT4+ LOUT4GND LIN4+ LIN4GND GND OUTOUT+ GND LOCK
Typical Operating Circuit appears at end of data sheet.
LOUT1+ GND GND ININ+ GND CLKEN
MAX3754 MAX3755
31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23
CDREN RATESEL
CF+ CF-
VCC SEL1 SEL2
SEL3 SEL4 VCC
VCC
TQFP-EP*
*EXPOSED PAD MUST BE CONNECTED TO GROUND
Ordering Information
PART MAX3754CCM MAX3755CCM TEMP RANGE 0C to +70C 0C to +70C PIN-PACKAGE 48 TQFP-EP 48 TQFP-EP DIFFERENTIAL LIN AND LOUT TERMINATION 150 100 DIFFERENTIAL IN AND OUT TERMINATION 100 100
________________________________________________________________ Maxim Integrated Products
VCC
24
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
ABSOLUTE MAXIMUM RATINGS
VCC ...........................................................................-0.5V to +5V Current into OUT, LOUT1, LOUT2, LOUT3, LOUT4.......................................................... 22mA Voltage at OUT, LOUT1, LOUT2, LOUT3, LOUT4 .....................(VCC - 1.65V) to (VCC + 0.5V) Voltage at IN, LIN1, LIN2, LIN3, LIN4......................................................-0.5V to (VCC + 0.5V) Voltage at CLKEN, CF+, CF-, CDREN, RATESEL, SEL_, LOCK............................................-0.5V to (VCC + 0.5V) Current into LOCK...............................................-1mA to +10mA Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 30.0mW/C above +70C) ...........2W Operating Junction Temperature Range ...........-55C to +150C Operating Temperature Range .........................-55C to +110C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047F, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER CDREN = GND Supply Current (Note 1) CDREN = VCC Input Data Rate Range Differential Input Voltage Swing Input Common-Mode Voltage Differential Output Voltage Swing Differential L-Port Input Resistance Differential L-Port Output Resistance Differential Input Resistance at IN Differential Output Resistance at OUT TTL Low Input Voltage TTL High Input Voltage TTL Input Current LOCK Output Low Voltage LOCK Output High Voltage Differential Voltage across CF Data Propagation Delay IN to OUT, SEL_ = GND, CDREN = VCC LIN(n) to LOUT(n+1), LIN4 to OUT 0 TTL input voltages VCC IOL = +1mA (sinking) IOH = -100A (sourcing) 2.4 VCC 3 1 2 -50 50 0.4 RLOAD = RSOURCE MAX3754 MAX3755 MAX3754 MAX3755 1000 118 78 118 78 78 78 CONDITIONS MAX3754 MAX3755 MAX3754 MAX3755 -100 -100 200 VCC 0.45 1400 150 100 150 100 100 100 1800 182 122 182 122 122 122 0.8 MIN TYP 245 285 308 349 MAX 285 334 362 411 +100 +100 2200 ppm mVP-P V mVP-P V V A V V V ns mA UNITS
1.0625Gbps operation, RATESEL = GND 2.125Gbps operation, RATESEL = VCC
2
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Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047F, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER Channel Select Delay to Data Valid Data Transition Time Supply Noise Tolerance (Note 2) CDR Lock Time OPERATION AT 2.125Gbps (Note 3) Pattern = K28.7, CDREN = GND (Note 4) Random Jitter at OUT, Pattern = K28.7, CDREN = VCC L-Port Outputs Pattern = CRPAT, CDREN = VCC (Notes 5, 6) Pattern = K28.5+, CDREN = GND (Note 7) Deterministic Jitter at OUT, L-Port Outputs Total Jitter at OUT, LOUT_ Sinusoidal Component of Jitter Tolerance (BER = 10-12) Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking (Note 12) 1.7 5.4 3.8 27 19 37 1.5 0.1 0.1 UI 60 50 75 135 psP-P psP-P psRMS OPERATION AT 1.0625Gbps (Note 3) Pattern = K28.7, CDREN = GND (Note 4) Random Jitter at OUT, Pattern = K28.7, CDREN = VCC L-Port Outputs Pattern = CRPAT, CDREN = VCC (Notes 5, 6) Pattern = K28.5+, CDREN = GND (Note 7) Deterministic Jitter at OUT, L-Port Outputs Total Jitter at OUT, LOUT_ Sinusoidal Component of Jitter Tolerance (BER = 10-12) Pattern = K28.5+, CDREN = VCC Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) f = 42.5kHz sine wave Pattern = CJTPAT (Notes 6, 10) f = 635kHz sine wave f = 5MHz sine wave Pattern = K28.5+, CDREN = VCC Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) f = 85kHz sine wave Pattern = CJTPAT (Notes 6, 10) CJTPAT (Note 10) Pattern = CJTPAT (Notes 6, 10, 11) f = 1.27MHz sine wave f = 10MHz sine wave 1.5 0.1 0.1 0.4 0.7 6 10 0.05 UI UI MHz dB UI CONDITIONS SEL(n) to LOUT(n+1) , SEL4 to OUT 20% to 80% 10Hz f < 100Hz 100Hz f < 1MHz 1MHz f < 2.5GHz 65 MIN TYP 9 110 100 40 10 530 1.6 4.1 3 29 19 28 60 50 50 105 psP-P psP-P psRMS s mVP-P 160 MAX UNITS ns ps
MAX3754/MAX3755
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3
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047F, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking (Note 12) CONDITIONS CJTPAT (Note 10) Pattern = CJTPAT (Notes 6, 10, 11) MIN 0.4 0.7 3 5 0.05 TYP MAX UNITS UI UI MHz dB
Includes output currents. Meets jitter output specifications with noise applied. AC characteristics are guaranteed by design and characterization. K28.7 Pattern: 00 1111 1000 Compliant Random Pattern in hex (CRPAT): Pattern Sequence: Repetitions: 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 6: Parameter measured with 0.40UI deterministic and 0.20UI random jitter (BER = 10-12 ) applied to the input. All ports are bypassed, SEL_ = TTL low. Jitter is in compliance with the inter-enclosure, Fibre Channel jitter tolerance (at compliance point R) and jitter output (at compliance point T) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a non-zero jitter input. Note 7: K28.5 Pattern: 00 1111 1010 11 0000 0101 Note 8: Random Pattern in Hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65 Note 9: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 (bit-rate) by a 4th-order Bessel-Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the bit error rate exceeds 10-12. TJ can be estimated as TJ = DJ + (14 RJ). DJ is deterministic jitter. RJ is one sigma distribution (RMS) of random jitter. Note 10: Compliant Jitter Tolerance Pattern in Hex (CJTPAT): Pattern Sequence: Repetitions: 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 87 1E 38 71 E3 41 87 1E 38 70 BC 78 F4 AA AA AA 1 AA AA AA AA AA 12 AA A1 55 55 E3 87 1E 38 71 E1 1 AB 9C 96 86 E6 1 C1 6A AA 9A A6 1 Note 11: Parameter measured with 0.1UI sinusoidal jitter at 10MHz for 2.125Gbps data rate, or 5MHz for 1.0625Gbps. Note 12: Simulation shows peaking of 0.01dBm max. Characterization results limited by test equipment. Note 1: Note 2: Note 3: Note 4: Note 5:
4
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Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater
Typical Operating Characteristics
(VCC = +3.3V, CF = 0.047F, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERTURE (MAX3754)
MAX3754 toc01
MAX3754/MAX3755
OUTPUT EYE DIAGRAM AT OUT (1.0625Gbps CRPAT, CDR ENABLED)
MAX3754 toc02
OUTPUT EYE DIAGRAM AT OUT (2.125Gbps CRPAT, CDR ENABLED)
MAX3754 toc03
340 320 SUPPLY CURRENT (mA) CDR ENABLED 300 280 260 240 220 200 0 10 20 30 40 50 60 CDR DISABLED
200mV/ div
INPUT = 400mVP-P DJ = 0.4UI RJ = 0.2UI
200mV/ div
INPUT = 400mVP-P DJ = 0.4UI RJ = 0.2UI
70
200ps/div
100ps/div
TEMPERATURE (C)
OUTPUT JITTER BATHTUB PLOT (1.0625Gbps)
1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 0 1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 0
MAX3754 toc04
OUTPUT JITTER BATHTUB PLOT (2.125Gbps)
2.125Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI)
MAX3754 toc05
BIT ERROR RATE
1.0625Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI)
BIT ERROR RATE
0.2
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
JITTER TOLERANCE 1.0625Gbps
MAX3754 toc06
JITTER TOLERANCE 2.125Gbps
CJTPAT DJ = 0.4UI RJ = 0.2UI 1
MAX3754 toc07
10 CJTPAT DJ = 0.4UI RJ = 0.2UI 1
10
SINUSOIDAL JITTER (UIP-P)
FIBRE CHANNEL MASK 0.1
SINUSOIDAL JITTER (UIP-P)
FIBRE CHANNEL MASK 0.1
0.01 10k 100k 1M 10M FREQUENCY (Hz)
0.01 10k 100k 1M 10M FREQUENCY (Hz)
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5
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
Pin Description
PIN 1, 4, 7, 8, 11, 26, 29, 30, 33, 36, 39, 42, 43, 46 2 3 5 6 9 10 12 13, 16, 21, 24 14 15 17 18 19 20 22 23 25 27 28 31 32 34 35 37 38 40 41 44 45 47 48 EP NAME GND LIN1LIN1+ LOUT1LOUT1+ ININ+ CLKEN VCC CF+ CFSEL1 SEL2 SEL3 SEL4 CDREN RATESEL LOCK OUT+ OUTLIN4LIN4+ LOUT4LOUT4+ LIN3LIN3+ LOUT3LOUT3+ LIN2LIN2+ LOUT2LOUT2+ Exposed Pad Electrical Ground Inverted Data Input for L-Port 1 Noninverted Data Input for L-Port 1 Inverted Data Output for L-Port 1 Noninverted Data Output for L-Port 1 Inverted Data Input Noninverted Data Input Clock Enable. A TTL high level enables clock output at L-Port 1. Supply Voltage CDR Filter Capacitor Positive Connection. CF = 0.047F. CDR Filter Capacitor Negative Connection. CF = 0.047F. Select 1. A TTL low on SEL1 selects data from IN. TTL high on SEL1 selects data from LIN1. Select 2. A TTL low on SEL2 selects data from the previous port bypass circuit. A TTL high on SEL2 selects data from LIN2. Select 3. A TTL low on SEL3 selects data from the previous port bypass circuit. A TTL high on SEL3 selects data from LIN3. Select 4. A TTL low on SEL4 selects data from the previous port bypass circuit. A TTL high on SEL4 selects data from LIN4. CDR Enable Input (TTL). A high input enables the CDR for data recovery. A low input disables the CDR (no data recovery). Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation. Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequencylocked. The output of the LOCK pin may chatter when large jitter is applied to the input. Noninverted Data Output Inverted Data Output Inverted Data Input for L-Port 4 Noninverted Data Input for L-Port 4 Inverted Data Output for L-Port 4 Noninverted Data Output for L-Port 4 Inverted Data Input for L-Port 3 Noninverted Data Input for L-Port 3 Inverted Data Output for L-Port 3 Noninverted Data Output for L-Port 3 Inverted Data Input for L-Port 2 Noninverted Data Input for L-Port 2 Inverted Data Output for L-Port 2 Noninverted Data Output for L-Port 2 The exposed pad must be soldered to the circuit board ground for proper thermal performance. DESCRIPTION
6
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Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
0.047F
CF+ RATESEL
CFLOCK
IN+ INCDREN CLKEN
100
PHASE/FREQ DETECTOR
LOOP FILTER
VCO /2
1 0
D
Q
1 0 0 1
0 1
0 1
0 1
0 100 1
OUT+ OUT-
LOUT1+ LOUT1-
LOUT2+ LOUT2-
LOUT3+ LOUT3-
LOUT4+ LOUT4-
LIN1+ LIN1-
LIN2+ LIN2-
LIN3+ LIN3-
LIN4+ LIN4-
SEL1
SEL2
SEL3
Figure 1. MAX3754/MAX3755 Functional Diagram
Detailed Description
The MAX3754/MAX3755 quad port bypass circuits (PBCs) consist of an input buffer, a rate-selectable clock and data recovery (CDR) circuit (for optional jitter attenuation), four serially connected port bypass circuits, and an output buffer (Figure 1). The circuit design is optimized for both 1.0625Gbps and 2.125Gbps operation at 3.3V.
Input Buffer
The input buffer provides line termination and level conversion. It accepts a differential input voltage of 200mV to 2200mV at IN. Internal resistors terminate the inputs to 100 differentially eliminating the need for external resistors.
The input buffer drives the CDR circuit, as well as one input of a 2:1 multiplexer. A TTL high on CDREN enables the CDR and connects the CDR data output to the port bypass circuits. The recovered clock signal is available for test purposes at LOUT1 when CLKEN is asserted high. A TTL low on CDREN disables the CDR and connects the output of the input buffer directly to the port bypass circuits. A RATESEL pin is included to switch the CDR between data rates. The VCO output has a divide-by-2 block that is switched into the PLL when RATESEL is TTL low for 1.0625Gbps operation (see Figure 1). Phase and Frequency Detector The frequency difference between the VCO clock and the received data is derived by sampling the in-phase and quadrature VCO outputs on the edges of the input data signal. The frequency detector drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. The PLL drives this error voltage to zero, aligning the recovered clock to the center of the incoming eye.
7
Clock and Data Recovery
The purpose of the CDR is to improve jitter transfer performance by attenuating jitter that may be present in the input data. The CDR can recover 1.0625Gpbs or 2.125Gbps data signals that are corrupted by up to 0.7UI of high-frequency jitter (BER = 10-12 ). When jitter attenuation is not needed, the CDR may be disabled in order to save power.
_______________________________________________________________________________________
SEL4
OPTIONAL 100 OR 150 TERMINATION FOR LOUT AND LIN
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
Loop Filter, VCO, and Latch The phase detector and frequency detector outputs are summed into a loop filter. An external capacitor (between CF+ and CF-) is required to set the PLL damping factor. The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of VCC noise. The VCO creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing output jitter. LOCK Output An active high LOCK output monitor derived from the frequency detector indicates that the PLL is frequency locked onto the input data. Without input data, the LOCK signal may settle at TTL High or TTL Low. The use of a low-pass RC filter is recommended to reduce the effects of chatter that could be caused by a high input jitter content. RATESEL Input The RATESEL input is used to select between input data rates of 2.125Gbps and 1.0625Gbps. This function allows the repeater to sample data at the correct data rate by selecting an optional a divide-by-2 network. RATESEL selects between the VCO tuned frequency and half that frequency, allowing maximum jitter tolerance at both data rates. The loop bandwidth of the repeater scales with the selected frequency; i.e., the loop-bandwidth at an input rate of 1.0625Gbps is half that at the input rate of 2.125Gbps.
Output Buffer
The output signal of the last PBC drives the differential high-power output buffer. The output buffer drives the output port (OUT). Internal resistors terminate each output with 50 to VCC (100 differentially), eliminating the need for external termination resistors. The output buffer produces a differential peak-to-peak output voltage of 1V to 1.8V when driving a differential load.
Applications Information
The MAX3754/MAX3755 quad-PBC is designed for hard-disk array applications using the Fibre Channel Arbitrated Loop network protocol. In applications where data storage reliability is critical, it may be desirable to create a disk array where the data is stored redundantly on more than one physical drive. The Fibre Channel Arbitrated Loop protocol enables multiple physical drives to be connected in a loop topology. Each physical drive is connected to the Fibre Channel loop through an L-port that may be individually addressed and controlled to create an array of logical drives. Data is transmitted over the loop as an encoded serial bit stream. Using the Fibre Channel Arbitrated Loop protocol, the configuration of the disk array can be rearranged under software control to achieve desired objectives (such as data reliability or fast access). The port bypass circuit allows any L-port to be enabled (connected to the loop) or bypassed (disconnected from the loop) while the loop is operating. This enables hot swapping of physical drives (inserting or removing physical drives while the loop is operating) so that drives may be replaced with minimal disruption to the disk array system. Figure 2 shows a disk array.
Port Bypass Circuits
The output of the 2:1 input multiplexer drives a cascaded series of four PBCs. Each PBC consists of a differential output buffer, a differential input buffer, and a 2:1 multiplexer. The multiplexer select input (SEL_) controls whether a port is included in the loop. A TTL low on a multiplexer select pin routes the data signal from the previous stage to the multiplexer output (port bypass mode). A TTL high on the multiplexer select pin routes the data signal from the input buffer to the multiplexer output (port enable mode). The output of the last PBC drives the output buffer. The MAX3754 has 150 differential termination on the inputs and 75 single-ended terminations to VCC on the outputs (see Input/Output Structures for specifics) of the L-ports to match Fibre Channel Arbitrated Loop specifications. The MAX3755 is terminated with 100 and 50, respectively. Testing a MAX3754 using standard 50 test equipment requires an impedance matching network
8
Filter Capacitor Requirements
The MAX3754/MAX3755 phase lock loop's (PLL) filter capacitor is required to be supplied in a port bypass design. This capacitor sets the damping factor of the device. It also determines how fast the PLL can acquire initial lock. This device is specified and tested with the recommended filter capacitor value of 0.047F that limits transfer peaking.
Input/Output Structures
Figures 3 and 4 show models for the MAX3754/ MAX3755 inputs and outputs, modeling package parasitics, and ESD diodes.
Cascading Port Bypass Circuits
Two or more MAX3754/MAX3755 quad-PBCs can be cascaded by directly connecting the OUT pins of one
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Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
IN IN FC-AL DRIVES PORT CONTROL PORT CONTROL
Figure 2. Disk Array Implemented with Port Bypass Circuits
_______________________________________________________________________________________
FAIL-OVER LOOP MAX3750 PBC OUT
PRIMARY LOOP
REPEATER
REPEATER MAX375x PBC REPEATER MAX375x PBC REPEATER MAX375x PBC
MAX377x
MAX377x
MAX377x
MAX377x
MAX375x PBC
MAX377x
MAX377x
REPEATER
MAX377x
MAX377x
MAX375x PBC
MAX377x
MAX377x
MAX377x
MAX377x
REPEATER
MAX377x
MAX377x
MAX375x PBC
MAX377x
MAX377x
MAX377x
MAX377x
MAX3750 PBC 0
MAX377x
MAX377x 1 OUT
9
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
PACKAGE PARASITICS DIE VCC
ESD STRUCTURES
1.2k
2.2nH 0.2pF 0.4pF
2.2nH 0.2pF 0.4pF
50 *(75)
50 *(75)
VCC - 0.45V
*MAX3754 LIN_ INPUTS
Figure 3. MAX3754/MAX3755 Input Structure
VCC DIE
quad-PBC to the IN pins of the next quad-PBC. See Typical Operating Circuit.
PACKAGE PARASITICS ESD STRUCTURES 2.2nH OUT+ 0.4pF 2.2nH OUT0.4pF 0.2pF 0.2pF
Layout Considerations
For best performance, carefully lay out the PC board using high-frequency techniques. Filter voltage supplies, keep ground connections short with multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3754/MAX3755 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed very close to VCC pins. Isolate the input signals from the output signals as much as possible.
50 *(75)
50 *(75)
*MAX3754 LOUT_ OUTPUTS
Figure 4. MAX3754/MAX3755 Output Structure 10 ______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
Typical Operating Circuit
DISK DRIVE L_PORT n IN OUT SEL DISK DRIVE L_PORT n+1 IN OUT SEL DISK DRIVE L_PORT n+4 IN OUT SEL DISK DRIVE L_PORT n+5 IN OUT SEL
LOUT1
LOUT2
LOUT1
LIN1
LIN2
LIN1
LOUT2
LIN2
SEL1
SEL2
SEL1
VCC VCC UPSTREAM L_PORT GND IN+ INCF 0.047F CF+
VCC
SEL2
VCC VCC GND Z0 = 50 Z0 = 50 CF 0.047F IN+ INCF+
VCC DOWNSTREAM L_PORT
CDREN LOCK OUT+
CDREN LOCK OUT+
MAX3754 MAX3755
OUTCLKEN
MAX3754 MAX3755
OUTCLKEN
LOUT3
LOUT4
LOUT3
LOUT4
CF-
RATESEL LIN4 SEL4
CF-
RATESEL LIN4 DISK DRIVE SEL4
LIN3
LIN3
SEL3
IN OUT SEL L_PORT n+2 DISK DRIVE
IN OUT SEL L_PORT n+3 DISK DRIVE
SEL3
IN OUT SEL L_PORT n+6 DISK DRIVE
IN OUT SEL L_PORT n+7
NOTE: ALL HIGH-SPEED INPUTS AND OUTPUTS (IN, OUT, LIN, AND LOUT) SHOULD BE CONNECTED USING CONTROLLEDIMPEDANCE TRANSMISSION LINES. AC-COUPLING MAY ALSO BE REQUIRED. ALL CAPACITORS ARE 0.1F UNLESS OTHERWISE INDICATED. FIGURE SHOWS 1.0625Gbps OPERATION. FOR 2.125Gbps OPERATION, CONNECT RATESEL TO VCC.
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11
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12
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48L,TQFP.EPS
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3754/MAX3755
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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